Generalized Low-voltage Circuit Techniques for Very High-speed Time-interleaved Analog-to-digital Converters
by Sin, Sai-weng; U, Seng-pan; Martins, Rui PauloFormat: Hardcover
Pub. Date: 2010-11-12
Publisher(s): Springer Verlag
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Summary
Analog-to-Digital Converters (ADCs) play an important role in most modern signal processing and wireless communication systems where extensive signal manipulation is necessary to be performed by complicated digital signal processing (DSP) circuitry. This trend also creates the possibility of fabricating all functional blocks of a system in a single chip (System On Chip - SoC), with great reductions in cost, chip area and power consumption. However, this tendency places an increasing challenge, in terms of speed, resolution, power consumption, and noise performance, in the design of the front-end ADC which is usually the bottleneck of the whole system, especially under the unavoidable low supply-voltage imposed by technology scaling, as well as the requirement of battery operated portable devices. Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters will present new techniques tailored for low-voltage and high-speed Switched-Capacitor (SC) ADC with various design-specific considerations.
Table of Contents
| Introduction | p. 1 |
| Low-Voltage High-Speed Analog-to-Digital Conversion | p. 1 |
| Applications of High-Speed ADCs | p. 3 |
| Deep-Submicron CMOS ADCs Designs | p. 5 |
| Main Objective and Design Challenges | p. 7 |
| References | p. 8 |
| Challenges in Low-Voltage Circuit Designs | p. 11 |
| Introduction | p. 11 |
| The Impact of CMOS Technology Scaling | p. 11 |
| Design Challenges: Intrinsic Performance Degradation | p. 13 |
| Transconductance Degradation | p. 13 |
| Output Resistance Degradation | p. 14 |
| Trends of Unity-Gain Frequency in Technology Scaling | p. 15 |
| Circuit Level Design Challenges: Opamps | p. 15 |
| Circuit Level Design Challenges: Switches | p. 17 |
| Switch Positioning | p. 19 |
| Clock Boosting | p. 19 |
| Bootstrapped Switches | p. 20 |
| Switched-Opamp | p. 21 |
| Reset-Opamp | p. 22 |
| Switched-RC Techniques | p. 23 |
| Summary | p. 24 |
| References | p. 25 |
| Advanced Low Voltage Circuit Techniques | p. 27 |
| Introduction | p. 27 |
| Virtual-Ground Common-Mode Feedback and Output Common-Mode Error Correction | p. 28 |
| Low-Voltage CMFB Design Challenges | p. 28 |
| Novel Virtual Ground CMFB Technique | p. 29 |
| Practical Implementation of VG-CMFB | p. 31 |
| Output Common-Mode Error Correction | p. 32 |
| Cross-Coupled Passive Sampling Interface | p. 33 |
| Problems in Existing Solutions | p. 33 |
| Cross-Coupled Passive Sampling Interface | p. 35 |
| Voltage-Controlled Level Shifting | p. 39 |
| Feedback Current Biasing Technique | p. 40 |
| Low-Voltage Finite-Gain-Compensation | p. 43 |
| The Need for Finite-Gain Compensation | p. 43 |
| Auxiliary Differential-Difference Amplifier | p. 47 |
| Low-Voltage Offset-Compensation | p. 49 |
| The Crossed-Coupled S/H | p. 49 |
| The SC Amplifier | p. 51 |
| Summary | p. 52 |
| References | p. 53 |
| Time-Interleaving: Multiplying the Speed of the ADC | p. 55 |
| Introduction | p. 55 |
| Time-Interleaved ADC Architecture | p. 55 |
| Channel Mismatch Analysis | p. 57 |
| Offset Mismatch | p. 61 |
| Gain Mismatch | p. 63 |
| Timing Mismatch | p. 66 |
| Bandwidth Mismatch | p. 68 |
| Summary | p. 72 |
| References | p. 73 |
| Design of a 1.2 V, 10-bit, 60-360 MHz Time-Interleaved Pipelined ADC | p. 75 |
| Introduction | p. 75 |
| The Overall ADC Architecture | p. 76 |
| Prototype Circuit-Level Design | p. 77 |
| Resistively Demultiplexed Front-End Sample-and-Hold | p. 77 |
| 1.5 b/Stage Multiplying-Digital-to-Analog-Converter (MDAC) | p. 78 |
| Current-Mode Sub-ADC Design | p. 80 |
| Programmable Timing-Skew Insensitive Clock Generator | p. 81 |
| Noise Analysis | p. 82 |
| Channel Mismatch Analysis | p. 85 |
| Layout Considerations | p. 86 |
| Simulation Results | p. 88 |
| Opamp Simulations | p. 88 |
| Front-End S/H | p. 88 |
| Current-Mode Comparator | p. 90 |
| The Overall ADC Simulations | p. 92 |
| Summary | p. 94 |
| References | p. 94 |
| Experimental Results | p. 97 |
| Introduction | p. 97 |
| The Prototype PCB Design | p. 97 |
| The Floor Plan | p. 97 |
| Power Supply Considerations | p. 98 |
| Signal Trace Routing | p. 100 |
| Measurement Setup and Results | p. 100 |
| Time-Domain Digital Output Code Pattern | p. 102 |
| Static Performance | p. 102 |
| Dynamic Performance | p. 104 |
| Summary | p. 108 |
| References | p. 111 |
| Conclusions and Prospective for Future Work | p. 113 |
| Conclusions | p. 113 |
| Prospective for Future Work | p. 114 |
| Low-Noise and Low-Voltage Circuit Techniques Implementation | p. 115 |
| Fully Dynamic ADC Implementations | p. 115 |
| SC Circuits Implemented with Open-Loop Amplifiers | p. 115 |
| Digital Calibration | p. 116 |
| References | p. 116 |
| Operating Principle of VG-CMFB with O-CMEC | p. 117 |
| Mathematical Analysis of Bandwidth Mismatches | p. 121 |
| Noise Analysis of Advanced Reset-Opamp Circuits | p. 125 |
| Cross-Coupled Front-End S/H | p. 125 |
| MDAC with Auxiliary Amplifier | p. 126 |
| Special Case in Gain Mismatch | p. 131 |
| Index | p. 133 |
| Table of Contents provided by Ingram. All Rights Reserved. |
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