Nano-CMOS Design for Manufacturability Robust Circuit and Physical Design for Sub-65nm Technology Nodes,9780470112809

Nano-CMOS Design for Manufacturability Robust Circuit and Physical Design for Sub-65nm Technology Nodes

by ; ; ; ; ;
Edition: 1st
ISBN13: 9780470112809
ISBN10: 0470112808
Format: Hardcover
Pub. Date: 2008-10-20
Publisher(s): Wiley-Interscience
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Summary

This book is the sequel to Nano-CMOS Circuit and Physical Design, taking design to technology nodes beyond 65nm geometries. It examines the challenges that design engineers face in the nano-scaled era, such as exacerbated effects and the proven design for manufacturability (DFM) methodology in the midst of increasing variability and design process interactions. It also tackles complex issues in the design process and introduces several emerging concepts, including stress proximity effects, contour-based extraction, and design process interactions.

Author Biography

Ban P. Wong, CEng, MIET, is Director of Design Methodology at Chartered Semiconductor, Inc. He holds five patents and is the lead author of Nano-CMOS Circuit and Physical Design (Wiley). Franz Zach, PhD, is Senior Director at PDF Solutions, where he is involved in integrated yield ramps at advanced technology nodes. Victor Moroz, PhD, is a Principal Engineer at Synopsys. He focuses on semiconductor physics, including silicon process integration, teaching undergraduate and graduate students, and developing process simulation and DFM tools. Anurag Mittal, PhD, codeveloped the world's first truly CMOS-compatible Flash technology. He has several papers, invited talks, and patents to his credit. Greg W. Starr, PhD, is a Supervising Principal Engineer at Xilinx, where he is responsible for advanced serial IO development on advanced processes. Andrew Kahng, PhD, is Professor of CSE and ECE at the University of California, San Diego, and the CTO of Blaze DFM. His research focuses on integrated circuit physical design and design for manufacturability. Dr. Kahng has published more than 300 journal and conference papers.

Table of Contents

Introduction
DFM - Value proposition
Deficiencies in Boolean-based Design Rules in the sub-wavelength regime [6]
Impact of Variability on Yield and Performance
The industry challenge - disappearing process window
Mobility enhancement techniques - a new source of variability induced by design process interaction
Design dependency of chip surface topology
Newly exacerbated narrow width effect in nano-CMOS nodes
Well proximity effect
Scaling beyond 65nm drives the need for model based DFM solutions
Summary
Newly Exacerbated Effects
Lithography related Aspects of DFM
Economic motivations for DFM
Lithographic tools and techniques for advanced technology nodes
Lithography limited yield
Lithography driven DFM Solutions
Interaction of layout with transistor performance and stress engineering techniques
Introduction
Impact of stress on transistor performance
Stress propagation
Stress sources
Introducing stress into transistors
Design Solutions
Signal and Power Integrity
Introduction
Interconnect Resistance, Capacitance and Inductance
Inductance Effects on Interconnect
Analog and Mixed Signal Circuit Design for Yield and Manufacturability
Introduction
Guidelines
Device Selection
Device Size Heart Beat
Device Matching
Design Guidelines
Layout Guidelines
Test
Design for Variability, Performance and Yield
Introduction
Impact of variations (introduced by both process and circuit operation) on the design
Some Parametric Fluctuations with new implications for design
Process Variations in Interconnects
Impact of Deep Sub-Micron Integration in SRAMs
Impact of Layout Styles on Manufacturability, Yield and Scalability
Design for variations
Summary
The Road To Dfm
Nano-CMOS design tools: Beyond model-based analysis and correction
Introduction
Electrical Design for Manufacturability (DFM)
Criticality Aware DFM
On Guardbands, Statistics, and Gaps
Opportunistic Mindsets
Futures at รณ 45nm
Summary
References
Table of Contents provided by Publisher. All Rights Reserved.

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